Verification Engineer

You will

• Take full responsibility for verification of a design, being block or sub-system
• Define and implement UVM based test environments
• Break-down Requirements and create Verification Specifications, including verification strategy for the design object and associated verification plan
• Executing Verification Strategy, with creating UVM test benches
• Develop, run and debug test cases
• Work with Coverage Closure to reach Quality goals
• Continuously improve and optimize ways of working
• Generate documentation
• Develop competence in technical domain

To be successful in the role you must have:

• A MSc degree in a technical field or the equivalent level of education
• 8+ years’ experience from verification using System Verilog and UVM.
• Experience in developing verification test plans and directed/randomized test cases
• Good team cooperation skills
• Good communication in English
• Skills in result-driven and meet expectations

Additional Requirements:

• Experience using Cadance verification suite
• Experience using vManager and vPlans
• Experience from Formal Verification